1. Technical Field
The present invention generally relates to frequency synthesizers for wired or wireless communications and, more particularly, to a phase locked loop (PLL) that includes a control circuit for reducing lock-time.
2. Description of Related Art
A digital frequency synthesizer is a phase locked loop (PLL) which is capable of outputting a wide range of frequencies by adjusting the values of a programmable counter. Such a PLL has been used in communication systems such as ham radios, wireless phones, and in airplanes. In general, the digital frequency synthesizer generates an output signal which is an integer multiple of a reference input frequency input thereto.
FIG. 1 is a block diagram illustrating an embodiment of a basic frequency synthesizer used in communications, according to the prior art. The frequency synthesizer includes a microcomputer (MICOM) 11, a crystal oscillator (X-OSC) 12, a phase locked loop (PLL) 100, a receiver-voltage-controlled oscillator (RX-VCO) 13 and a transmitter-voltage-controlled oscillator (TX-VCO) 14. The microcomputer 11 outputs two series of data D/D and En and a control clock (CLK) signal which are used for controlling the PLL 100. The serial data D/D is a signal having information corresponding to the reception division ratio, the reference division ratio and the transmission division ratio. The other serial data En is a signal that includes a reception enable signal, a reference enable signal and a transmission enable signal. According to the control clock (CLK), the serial data D/D and En are input into the PLL 100.
The crystal oscillator 12 is a source of reference frequency signal X/O whose frequency and phase are compared to that of an output signal R/V of the receiver voltage-controlled oscillator 13 and an output signal T/V of the transmitter-voltage-controlled oscillator 14.
The receiver-voltage-controlled oscillator 13 is used in the case when a wired/wireless phone is in a reception mode, and the transmitter-voltage-controlled oscillator 14 is used in the case when a wired or wireless phone is in a transmitting mode.
The PLL 100 is used to stabilize the outputs of voltage-controlled oscillators 13 and 14 at an appropriate frequency so that a wired or wireless phone system can be operated at a normal operating frequency. The PLL includes a latch 111, a reception divider 112, a reference divider 113, a transmission divider 114, a first phase detector 115 and a second phase detector 116.
The latch 111 receives the two serial data signal D/D and En and the control clock CLK from the microcomputer 11 and then outputs a reception division data signal RXDD, a reference division data signal REFDD, a transmission division data signal TXDD, a reception enable signal RXEN, a reference enable signal REFEN and a transmission enable signal TXEN.
The reception divider 112 receives the reception division data RXDD in response to the reception enable signal RXEN and divides the output signal R/V of the receiver-voltage-controlled oscillator 13 according to the reception division data signal RXDD.
The reference divider 113 receives the reference division data signal REFDD in response to the reference enable signal REFEN and divides the output signal X/O of the crystal oscillator 12 according to the reference division data signal REFDD.
The transmission divider 114 receives the transmission division data signal TXDD in response to the transmission enable signal TXEN and divides the output signal T/V of the transmitter-voltage-controlled oscillator 14 according to the transmission division data signal TXDD.
The first phase detector 115 receives an output signal FDRX of the reception divider 112 and the output signal FDREF of the reference divider 113 and then detects the difference in frequency and phase therebetween. The second phase detector 116 receives an output signal FDTX of the transmission divider 114 and the output signal FDREF of the reference divider 113 and then detects the difference in frequency and phase therebetween.
FIG. 2 is a view diagram illustrating waveforms of signals in the operation of the conventional PLL shown in FIG. 1. In this drawing, CLK is the system clock used in a wired or wireless communications system. Referring to FIG. 2, when a reception enable signal RXEN is logic high, an output signal FDRX of the reception divider 112 is generated. The output signal FDRX is the resultant signal generated by dividing the output signal R/V of the receiver-voltage-controlled oscillator 13 according to a division ratio of the reception division data signal RXDD.
When a transmission enable signal TXEN is logic high, an output signal FDTX of the transmission divider 114 is generated. When a reference enable signal REFEN is logic high, an output signal FDREF of the reference divider 113 is generated. The output signal FDTX is the resultant signal of dividing the output signal T/V of the transmitter-voltage-controlled oscillator 14 according to the division ratio of the transmission division data signal TXDD. The output signal FDREF is the resultant signal of dividing the output signal X/O of the crystal oscillator 12 according to a division ratio of the reference division data signal REFDD.
The first and second phase detectors 115 and 116 detect the frequency and phase differences among the output signals FDRX, FDREF and FDTX of the dividers 112, 113 and 114. Referring again to FIG. 2, the phase difference between the output signals FDRX and FDREF is indicated as RX-phase error and the phase difference between the output signals FDREF and FDTX is indicated as TX-phase error.
The RX-phase error and the TX-phase error are basically different from each other by the period of the enable signal EN. Accordingly, the phase difference between the two compared signals FDRX and FDREF or FDREF and FDTX is equal to the original phase difference between the two compared signals FDRX and FDREF or FDREF and FDTX added to the RX-phase error or the TX-phase error. Therefore, the lock-time of the PLL becomes longer.